In a digital TV receiver, a broadcast analog color video signal is applied to a conventional receiving antenna. The signal received by the antenna is processed by an analog tuner and intermediate frequency (IF) circuitry. A baseband composite video signal CVS from the IF circuitry is applied to an analog-to-digital (A/D) converter. The A/D converter develops binary or digital representations of the analog composite video signal CVS in response to a sampling or master clock signal MCS. The binary samples are processed in digital circuits to appropriately condition the luminance Y (luma) and chrominance C (chroma) components of the composite video signal CVS for application to the matrixing circuitry of the TV receiver. The Red (R), Green (G) and Blue (B) signals developed by the matrix circuits are converted back to the analog format for application to the kinescope.
For chroma demodulation, it is advantageous to set the frequency of the sampling clock signal MCS at four (4) times the color subcarrier rate F.sub.sc, and to phase lock the 4 F.sub.sc clock signal to the color burst signal BS incorporated in the incoming composite video signal CVS. Sampling the chrominance signal C using a 4 F.sub.sc burst locked clock (BLC) produces the following sample sequence: -(B-Y), -(R-Y), (B-Y), (R-Y), -(B-Y) and so on. Demodulation may be accomplished by merely demultiplexing the sample stream into separate (R-Y) and (B-Y) data streams.
However, for memory based features (e.g., pix-in-pix, freeze picture, zoom, recursive filtering, etc.), it is desirable to process the video signal with a line locked clock (LLC). A line locked clock produces a fixed integer number (e.g, 910) of sampling points per horizontal line. This simplifies memory based video features processing (e.g., line, field or frame memories), because the respective samples are vertically aligned (i.e., TV raster is orthogonally sampled).
For a standard NTSC video signal (e.g., broadcast TV signal), a sampling clock frequency, which is an even integer multiple of the color subcarrier frequency F.sub.sc, contains a fixed integer number of clock pulses in every horizontal line period. The color subcarrier frequency F.sub.sc is established at 455/2 times the horizontal line frequency F.sub.H (i.e., F.sub.sc =(455/2).times.F.sub.H) in a standard NTSC TV signal. A sampling clock frequency F.sub.MCS of 4 F.sub.sc has exactly 910 clock periods (4.times.455/2) in every horizontal line period. For a standard NTSC video signal, a clock signal may be concurrently burst locked and line locked, thereby facilitating both chroma demodulation and memory based applications (e.g., zoom).
However, not all NTSC compatible TV signals conform precisely to the NTSC broadcast standard format. For example, signals produced by a video cassette recorder (VCR) have varying horizontal line periods in the reproduced signal. This results in a variation in the number of clock pulses developed per horizontal line (e.g., 909.9, 910, 910.1, etc.). In general, for non-standard TV signals, it is not possible that a clock signal be simultaneously burst locked and line locked.
Two previously known approaches for processing non-standard TV signals in the digital domain employ either a burst locked clock or a line locked clock. The use of a burst locked clock simplifies chroma demodulation. However, a burst locked clock produces a variation in the number of clock pulses per horizontal line, and therefore, causes a line-to-line variation in the phase of the clock signal relative to the horizontal synchronizing component. The line-to-line phase variation of the clock signal relative to the horizontal sync signal causes misalignment of the respective picture elements (pixels) from successive lines of the TV raster, thereby requiring additional processing for memory-based applications.
In order to compensate for the line-to-line misalignment of the pixels before they are written into the memory in a burst locked clock system, the input signal samples are time shifted or skew corrected for the phase differences between the incoming horizontal sync pulses IHSP's and the sampling clock pulses MCSP's. Additionally, the signal samples read out from the memory are corrected for skew errors prior to their application to the RGB matrix of the TV receiver. U.S. Pat. No. 4,638,360, entitled "Timing Correction for a Picture-In-Picture Television System", describes illustrative circuitry for correcting timebase errors in the incoming and outgoing signals in a memory-based video signal processing system employing a burst locked clock.
Alternately, one may use a line locked clock for sampling non-standard TV signals. Although this simplifies video features processing (e.g., pix-in-pix), it complicates the chroma demodulation operation when the TV signal is non-standard. Refer to a paper presented by Tom Nillesen, entitled "Line Locked Digital Colour Decoding", at the International Conference on Consumer Electronics in June, 1985 in Chicago for details of a chroma demodulation apparatus that operates in a line locked clock system.
A commonly-assigned, currently-filed U.S. patent application, Ser. No. 032,258 filed in behalf of the same inventors, and entitled "Television Receiver Having a Skew Corrected Clock", describes still another approach for sampling a non-standard TV signal. An A/D converter generates digital samples of an incoming composite video signal CVS in response to a skew corrected master clock signal MCS. The skew corrected clock signal MCS has its phase adjusted at the start of every horizontal line period, and has a constant frequency that is a fixed multiple L (e.g., 4) of the color subcarrier frequency F.sub.sc between successive phase adjustments.